The present invention is related generally to the field of semiconductor memory devices, and more particularly, to static content addressable memory cells and methods for storing data therein.
Content addressable memories (CAMs) are used in a variety of applications requiring pattern matching operation on bits, such as virtual memory, data compression, caching, and table lookup applications. With the popularity of high speed networks, wired or wireless, on the rise, CAMs have been frequently employed in networking equipment, particularly routers and switches, computer systems and other systems that require content searching, such as in network-address filtering and translation by matching partial node address. For example, in network router or switch, CAM devices are used to store Internet Protocol (IP) addresses and routing instructions associated with each address. When an IP packet is received and the IP address obtained, the router must retrieve the routing information for the packet in order to send it on the most direct route to the desired IP address. By using a CAM memory device, the router can search the CAM for the desired IP address. That is, the CAM searches for the desired content, and if there is a match, the CAM returns the associated routing information.
CAM devices can store data much like conventional memory devices. Generally, an address is provided by a controller to the CAM device, the address is used to access a particular memory location within the CAM memory array, and then the content stored in the addressed memory location is retrieved from the memory array. However, as previously discussed, CAM devices provide the added functionality of being able to search the stored data for desired content. That is, in addition to simply storing data in its memory array, a CAM device can search the memory array based on compare data corresponding to the desired content. When the content stored in the CAM memory array does not match the compare data, the CAM device returns a no match indication. However, when the content stored in the CAM memory array matches the compare data, the CAM device outputs information associated with the content.
CAM storage cells have been implemented using dynamic random access memory (DRAM) cells, as well as static random access memory (SRAM) cells. One of the benefits of using a DRAM cell structure for CAM cells is that they are smaller in size relative to SRAM cells. However, as with conventional DRAM cells, such designed CAM cells need to be periodically refreshed in order to maintain the integrity of the data, as is well known. CAM devices designed with DRAM cells also require that the rows of the CAM device to be read sequentially, one row at a time, which is prohibitively slow. Moreover, due to the match circuit that is included with CAM cells, there are more leakage paths from the storage node. The techniques used in DRAM cells to reduce transfer gate leakage may not be readily available to CAM cell designs.
As previously mentioned, CAM cells have also been implemented using SRAM cell designs. Although larger in size than DRAM cells, SRAM cells provide the benefit of not needing to be refreshed to maintain data integrity. SRAM cells have been designed with six transistors (6T) as well as four transistors (4T). The 6T SRAM cells provide the benefit of having relatively low soft-error rates. xe2x80x9cSoft-errors,xe2x80x9d as known in the art, are those errors that are typically caused by power supply problems or alpha particles. Although 4T SRAM cells are smaller relative to their 6T counterparts, the 4T SRAM cells have higher soft-error rates. This issue is particularly significant with respect to CAM devices, since the data stored in the CAM memory array essentially represents a database of information. That is, the soft-error rate of conventional 4T SRAM cells may be unacceptable in the application of a CAM device. Consequently, choosing to design a CAM device using a 6T SRAM structure, which, as previously mentioned, are relatively larger, may be an acceptable compromise in light of the more significant issues that arise where the integrity of the data in the CAM cell is questionable.
Accordingly, there is a desire and need for an alternative CAM cell design that is relatively small and yet has acceptably low soft-error rates.
The present invention is directed to a static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second access transistors, each coupled between a data node of the latch and a respective data line. The gates of each access transistor is coupled to a word line such that when activated, the respective data node and data line are coupled. The CAM cell further includes a match circuit coupled to one of the complementary data nodes of the latch. The match circuit discharges a match line in response to a data value stored at the data node to which the match circuit is coupled and compare data present on the respective data line mismatching. Two of the CAM cells can be used to implement a full ternary CAM cell. In storing data in the CAM cell, a first one of the data nodes is charged and the other data node is coupled to ground. The capacitive coupling of the first data node assists in is maintained the charge state.